1. Field of Invention
The disclosure relates to chip package assembly, and specifically to a chip package assembly manufactured to maintain bond wire separation to prevent electrical shorts, and a corresponding method therefor.
2. Related Art
There has been a significant effort over the last several years to continue to reduce the size of electronics devices. As a consequence of this effort, chip packages have likewise become smaller, and the contents of those chip packages have been condensed. Therefore, bond wires that connect semiconductor dies within the chip package to the chip package fingers are manufactured to be extremely close to one another, which has increased the likelihood that electrical shorting will occur. Electrical shorts can cause substantial interference and data errors, as well as chip damage, and are therefore extremely detrimental to proper chip performance.
FIG. 1 shows some examples of chip package configurations having a high likelihood for electrical shorting. In FIG. 1A, a semiconductor die 110 is connected to a plurality of substrate fingers 130 by a plurality of bond wires 120. As the number of bond wires 120 increases, the pitch p between each of the bond wires 120 and/or fingers 130 decreases. Consequently, the bond wires 120 become arranged so close to each other that extremely small shifts from their originally-manufactured positions can cause contact with neighboring bond wires 120. This is an example of wire-to-wire shorting.
FIG. 1B illustrates a second example, in which a relatively small die 110 is positioned above a relatively large die 140. In order to make contact with the substrate fingers 130, the bond wires 120 that connect contacts 115 of the die 110 to the fingers 130 must travel a significant distance. Consequently, the bond wires 120 are prone to sagging, in which the weight of the bond wire pulls the bond wire down. Depending on the orientation of the package when sagging occurs, the bond wires 120 may short to each other (wire-to-wire shorting) or to the die 110 or 140 (wire-to-die shorting).
FIG. 1C illustrates a third example, in which the die 110 is positioned over the die 140. Bond wires 160 connect the contacts 145 of the die 140 to the contacts 130 of the substrate 150. Similarly, bond wires 120 connect the contacts 115 of the die 110 to the contacts 130 of the substrate 150 (For ease of illustration, only a single bond wire 120 is shown. However, any or all of the remaining contacts 115 may be connected to the remaining contacts 130 using a similar configuration). FIG. 1D illustrates a side view of the configuration shown in FIG. 1C. In this configuration, the die 110 and the die 140 may be positioned very close to each other, making the clearance between the bond wires 120 and the bond wires 160 very small. As such, sagging in the bond wires 120 may cause an electrical short with the bond wires 160.
FIG. 1E shows a modification to the configuration of FIGS. 1C and 1D. In this example, the bond wire 120 has a reverse-loop configuration, which is designed to provide greater clearance between the wire 120 and wire 160. However, although the clearance has been increased, the wire 120 is still prone to sagging, especially since the shape of the reverse-loop configuration leaves a long flat wire portion between contacts.
As these examples show, conventional chip packages suffer from the potential for electrical shorts. In addition, as device and chip package sizes continue to decrease, this problem will grow.